1. Field of the Invention
This invention relates to integrated circuit device manufacturing, and more particularly, to the manufacture of molded packages for a semiconductor integrated circuit chip.
2. Description of the Related Art
Integrated circuit chips are becoming more complex through higher circuit densities, which is achieved through use of smaller feature sizes in the construction of these circuits. Circuit feature sizes as small as 0.5-0.8 micron are now possible, with further reductions planned in the near future. With these higher densities, the thin film construction of stacked layers of metal conductors, insulating oxides, transistors, and various other such features of the integrated circuit chips, gives rise to mechanical and thermal stress management problems. These stresses are produced by the interaction of hard thermoplastic or thermoset plastic (such as epoxy) packaging material with the integrated circuit chips, and even relatively small stresses can damage the small features on these chips. Stresses on the integrated circuit chip may be induced by coefficient of expansion and modulus of elasticity differences between the materials used in construction of an integrated circuit (including any leadframe and wire bonds) and its surrounding molded package. These induced stresses often produce chip passivation cracking and metal conductor line shearing and breakage during temperature cycling or similar operating thermal stress tests. Such damage becomes evident with single layer metal conductor chips having areas as low as forty thousand square mils and can also appear with multiple layer metal conductor chips having areas as small as twenty thousand square mils. In general, larger chips are subjected to more stresses than are smaller ones.
Attempts to reduce the stresses on chips through the use of low modulus of elasticity polymeric coatings have been only partially successful. The polymeric coating typically has a high coefficient of thermal expansion and when the overcoated circuit is encapsulated with the hard thermoset or thermoplastic, damage can still result at the chip surface and to the electrical connections (wire or beam lead bonds) from the chip to the external package leads. The use of a direct encapsulating thermoset or thermoplastic molding compound with a lower modulus of elasticity and a better match of coefficients of thermal expansion, is not an option without sacrificing other desirable thermal, chemical, mechanical and electrical performance properties.
Prior art proposals to solve the stress problem include cavity packages in premolded configuration. These proposed premolded packages mostly have been based on high temperature thermoplastic materials, however, some reference has been made to the use of thermoset plastics. These cavity packages are molded around a leadframe prior to chip assembly and must be made acceptable for subsequent chip mount and bonding. This requires deflashing and/or precleaning to prepare the various parts of the leadframes for subsequent chip attachment and electrical connection or bonding operations. Such leadframe parts may include the chip attach pad and the inner ends of the lead fingers. The processes of making electrical bonds between the chip terminal (or bonding) pads to the external leads, especially wire bonding, require a clean surface free from organic residue such as molded flash. Flash is unwanted plastic adhering to parts of the leadframe where it does not belong, and is produced during the molding process. Deflashing (removal of flash) can be accomplished either by mechanical or chemical means. Both deflashing processes present problems for the integrated circuit device assembly process.
Mechanical deflash can do irreversible damage to the thin gold or silver plate on the chip attach pad and inner ends of the lead fingers. The plating is required to make good diffusion bonds between the bond wire, or interconnect leads, and the lead fingers, and to make a good mechanical and/or electrical connection between the chip and the chip attach pad. Also, after mechanical deflash, a cleaning process is required to ensure that the chip attach pad and lead fingers have the cleanliness required for good connections to be made.
Chemical deflash can be as detrimental as mechanical deflash if not done properly. The chemicals used for both thermoplastics and thermosets work on the principle of attacking the interface of the flash to the metal leadframe in order to loosen the flash. Effective cleanup is required to ensure the removal of all contaminants from within the package, including residues of the deflash chemicals. Residues and other contaminants left within the package can cause latent reliability problems as these contaminants can chemically attack the packaged integrated circuit.
An additional disadvantage of the premolded package centers on the molding material. Thermoplastics, even high temperature thermoplastics, pose some restrictions on which chip attach adhesives and bonding processes can be employed to assemble the packaged integrated circuit device. Heat can cause the thermoplastic packaging material to emit gasses which can adversely affect the bonding operations. Thus, to avoid this, the chip mount adhesive cure temperature must be kept to a minimum, thereby limiting the types of adhesives which can be used. Similar problems can also occur with thermoset packaging material.
A further problem with thermoplastics is caused by the instability and softness of the packaging material when it is heated beyond the glass transition temperature for the material. At the glass transition temperature the packaging material becomes softer and more unstable, and the coefficient of thermal expansion of the packaging material increases rapidly with increasing temperature above the glass transition temperature. Thus, it becomes difficult to form good bonds because of the softness and instability of the packaging material supporting the leadframe and chip. Again, similar problems can arise with the use of thermoset plastics as packaging material.
Thermoplastics and thermosets are poor conductors of heat, which makes it difficult to transfer heat through the packaging material, upon which the chip pad rests, to the chip where the heat is required for such bonding processes as thermosonic bonding. This automatically dictates that the bonding processes be ultrasonic or very low temperature thermosonic, neither of which is as effective, with respect to bonding speed, as thermosonic bonding is at two hundred plus degrees Centigrade.
A further disadvantage of premolded cavity packages is that the chip attach pad is in contact with the packaging material. The leadframe material (including chip pad) and the packaging material have differing coefficients of thermal expansion which contributes to stresses arising at the places of contact.
FIG. 1 illustrates the process flow for construction of integrated circuit devices using premolded packages. Starting with molding compound at 1 and leadframe material at 2, the bottom part of the package is molded around the leadframe at 3. The leadframe is deflashed as necessary at 4 and any chemical residues removed at 5. If the packaging material is thermoplastic, the wafers are sawed to produce chips at 6 and the chip is adhesively mounted to the chip attach pad at 7. Bonds, such as wire bonds, are formed at 9 and the final removal of foreign material is carried out at 14. A gel such as silicone is introduced within the cavity of the package at 15 to keep out moisture and is cured at 16. The package lid is cleaned at 17 and the lid seal adhesive is preformed at 18. The lid with adhesive preform in place is placed on the bottom part of the package to seal the package at 19 and the adhesive is cured at 20. The package receives its final trim and form at 21 and is marked and labeled at 22 and electrically tested at 23. It can be seen that the prior art process using a premolded cavity package involves a considerable number of expensive steps.
Other prior art approaches using cavity packages are all similar in that the chip attach pads are in contact with the packaging material, which gives rise to the problems mentioned above where the leadframe and package have differing coefficients of thermal expansion. As with the premolded package, unwanted stresses can be generated upon the chip attach pad by the touching package material. Also as before, the packaging material makes it difficult to transfer effectively heat through the package to the chip attach pad. Thus, ultrasonic or low temperature thermosonic bonding are the only interconnection method options.